1 citations · 2 across the 3 of their papers we have counts for
3 papers
Machine Learning Framework for Early Power, Performance, and Area Estimation of RTL
Anindita Chattopadhyay, Vijay Kumar Sutrakar
A critical stage in the evolving landscape of VLSI design is the design phase that is transformed into register-transfer level (RTL), which specifies system functionality through h…
A Novel Quaternary Decoder Design Utilizing 32nm CMOS and GNRFET Technology for Enhanced High-Density Memory Applications
Anindita Chattopadhyay, Pooja Desai, Vishwas P +1
Multi-Valued Logic (MVL) has more than one logic level defined to represent data whereas binary logic has 2 logic levels. It has been shown that the MVL circuits use the circuit re…
Fast and Accurate Identification of Hardware Trojan Locations in Gate-Level Netlist using Nearest Neighbour Approach integrated with Machine Learning Technique
Anindita Chattopadhyay, Siddharth Bisariya, Vijay Kumar Sutrakar
In the evolving landscape of integrated circuit design, detecting Hardware Trojans (HTs) within a multi entity based design cycle presents significant challenges. This research pro…