7 papers · 1 filter
TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog
Armin Abdollahi, Negin Ashrafi, Mehdi Kamal +1
Early, tool-free prediction of post-synthesis timing remains a key obstacle to rapid RTL iteration. We introduce TimingLLM, a two-stage retrieval-augmented LLM pipeline that estima…
HDLFORGE: A Two-Stage Multi-Agent Framework for Efficient Verilog Code Generation with Adaptive Model Escalation
Armin Abdollahi, Saeid Shokoufa, Negin Ashrafi +2
We present HDLFORGE, a two-stage multi-agent framework for automated Verilog generation that optimizes the trade-off between generation speed and accuracy. The system uses a compac…
SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics
Sasan Razmkhah, Mingye Li, Zeming Cheng +13
This research explores the use of superconductor electronics (SCE) for accelerating fully homomorphic encryption (FHE), focusing on the Number-Theoretic Transform (NTT), a key comp…
IC-D2S: A Hybrid Ising-Classical-Machines Data-Driven QUBO Solver Method
Armin Abdollahi, Mehdi Kamal, Massoud Pedram
We present a heuristic algorithm designed to solve Quadratic Unconstrained Binary Optimization (QUBO) problems efficiently. The algorithm, referred to as IC-D2S, leverages a hybrid…
SAIM: Scalable Analog Ising Machine for Solving Quadratic Binary Optimization Problems
Sasan Razmkhah, Jui-Yu Huang, Mehdi Kamal +1
This paper presents a CMOS-compatible Lechner-Hauke-Zoller (LHZ)--based analog tile structure as a fundamental unit for developing scalable analog Ising machines (IMs). In the desi…
MENAGE: Mixed-Signal Event-Driven Neuromorphic Accelerator for Edge Applications
Armin Abdollahi, Mehdi Kamal, Massoud Pedram
This paper presents a mixed-signal neuromorphic accelerator architecture designed for accelerating inference with event-based neural network models. This fully CMOS-compatible acce…