12 papers
Fair on the Surface? Benchmarking Hidden-Output Fairness Gaps in LLM Recommenders
Chan Aristella Lu, Arya Fayyazi, Junhao Zhang +6
Fairness audits for LLM-based recommenders have largely focused on observable outputs, implicitly assuming that stable recommendations reflect stable internal processing. We challe…
Multi-Level Modeling of Large Language Model Inference Latency and Energy via Hybrid Analytical--Machine-Learning Predictors
Saeid Shokoufa, Mohammad Erfan Sadeghi, Mehdi Kamal +1
The rapid scaling of Large Language Models (LLMs) has significantly increased computational cost, energy consumption, and inference latency, making accurate estimation essential fo…
COFT: Counterfactual-Conformal Decoding for Fair Chain-of-Thought Reasoning in Large Language Models
Arya Fayyazi, Mehdi Kamal, Massoud Pedram
Large language models (LLMs) can reveal and amplify societal biases during chain-of-thought (CoT) generation. We present COFT (Chain of Fair Thought), a training-free decoding meth…
TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog
Armin Abdollahi, Negin Ashrafi, Mehdi Kamal +1
Early, tool-free prediction of post-synthesis timing remains a key obstacle to rapid RTL iteration. We introduce TimingLLM, a two-stage retrieval-augmented LLM pipeline that estima…
HDLFORGE: A Two-Stage Multi-Agent Framework for Efficient Verilog Code Generation with Adaptive Model Escalation
Armin Abdollahi, Saeid Shokoufa, Negin Ashrafi +2
We present HDLFORGE, a two-stage multi-agent framework for automated Verilog generation that optimizes the trade-off between generation speed and accuracy. The system uses a compac…
SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics
Sasan Razmkhah, Mingye Li, Zeming Cheng +13
This research explores the use of superconductor electronics (SCE) for accelerating fully homomorphic encryption (FHE), focusing on the Number-Theoretic Transform (NTT), a key comp…