1 citations · 1 across the 8 of their papers we have counts for
10 papers
Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology
Wajid Ali, Muhammad Hadir Khan, Dalton Gaddy +1
Clock meshes are used in high-performance VLSI designs to minimize skew and tolerate on-chip variation, but they spend scarce routing resources on premium metal layers. Backside po…
HighTide: An Agent-Curated Open-Source VLSI Benchmark Suite
Benjamin Goldblatt, Paolo Pedroso, Farhad Modaresi +2
We introduce HighTide, an evolving AI-assisted benchmark suite. Specifically, the contributions are: (i) a diverse open-source suite spanning multiple design languages and technolo…
An Open-Source Flow for Single-Phase, Edge-Triggered to Two-Phase, Non-Overlapping Clocking Conversion
Paolo Pedroso, Lee-Way Wang, Matthew Guthaus
Two-phase clocking offers significant advantages in timing margin and clock flexibility, yet its adoption remains limited due to the absence of automation in modern design flows. M…
Heterogeneous Memory Design Exploration for AI Accelerators with a Gain Cell Memory Compiler
Xinxin Wang, Lixian Yan, Shuhan Liu +10
As memory increasingly dominates system cost and energy, heterogeneous on-chip memory systems that combine technologies with complementary characteristics are becoming essential. G…
OpenGCRAM: An Open-Source Gain Cell Compiler Enabling Design-Space Exploration for AI Workloads
Xinxin Wang, Lixian Yan, Shuhan Liu +10
Gain Cell memory (GCRAM) offers higher density and lower power than SRAM, making it a promising candidate for on-chip memory in domain-specific accelerators. To support workloads w…
GATMesh: Clock Mesh Timing Analysis using Graph Neural Networks
Muhammad Hadir Khan, Matthew Guthaus
Clock meshes are essential in high-performance VLSI systems for minimizing skew and handling PVT variations, but analyzing them is difficult due to reconvergent paths, multi-source…
Effective Capacitance Modeling Using Graph Neural Networks
Eren Dogan, Matthew R. Guthaus
Static timing analysis is a crucial stage in the VLSI design flow that verifies the timing correctness of circuits. Timing analysis depends on the placement and routing of the desi…
VLSI Hypergraph Partitioning with Deep Learning
Muhammad Hadir Khan, Bugra Onal, Eren Dogan +1
Partitioning is a known problem in computer science and is critical in chip design workflows, as advancements in this area can significantly influence design quality and efficiency…
GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNs
Bugra Onal, Eren Dogan, Muhammad Hadir Khan +1
The Rectilinear Steiner Minimum Tree (RSMT) problem is a fundamental problem in VLSI placement and routing and is known to be NP-hard. Traditional RSMT algorithms spend a significa…
OpenSpike: An OpenRAM SNN Accelerator
Farhad Modaresi, Matthew Guthaus, Jason K. Eshraghian
This paper presents a spiking neural network (SNN) accelerator made using fully open-source EDA tools, process design kit (PDK), and memory macros synthesized using OpenRAM. The ch…