10 citations · 15 across the 6 of their papers we have counts for
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cs.LG2025
Effective Capacitance Modeling Using Graph Neural Networks
Eren Dogan, Matthew R. Guthaus
Static timing analysis is a crucial stage in the VLSI design flow that verifies the timing correctness of circuits. Timing analysis depends on the placement and routing of the desi…
cs.LG2024
GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNs
Bugra Onal, Eren Dogan, Muhammad Hadir Khan +1
The Rectilinear Steiner Minimum Tree (RSMT) problem is a fundamental problem in VLSI placement and routing and is known to be NP-hard. Traditional RSMT algorithms spend a significa…