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cs.AR2026
VeriPilot: An LLM-Powered Verilog Debugging Framework
Yihan Wang, Cheng Liu, Jiazheng Zhang +4
Verilog debugging remains one of the most time-consuming stages in digital circuit design. Recent advances in Large Language Models (LLMs) have enabled automated debugging; however…
cs.AR2026
FT-Pilot: Automated Fault-Tolerant RTL Rewriting via Vulnerability-Guided LLMs
Weixing Liu, Zizhen Liu, Jing Ye +4
As integrated circuit technologies continue to scale toward advanced process nodes, the continual reduction in node capacitance and supply voltage has made digital systems increasi…