2 papers
cs.AR2026
Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators
Yuhao Liu, Salim Ullah, Akash Kumar
Neural network accelerators have been widely applied to edge devices for complex tasks like object tracking, image recognition, etc. Previous works have explored the quantization t…
cs.AR2025
Retrospective: A CORDIC Based Configurable Activation Function for NN Applications
Omkar Kokane, Gopal Raut, Salim Ullah +4
A CORDIC-based configuration for the design of Activation Functions (AF) was previously suggested to accelerate ASIC hardware design for resource-constrained systems by providing f…