2 papers
cs.AR2026
Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators
Yuhao Liu, Salim Ullah, Akash Kumar
Neural network accelerators have been widely applied to edge devices for complex tasks like object tracking, image recognition, etc. Previous works have explored the quantization t…
cs.AR2026
GRAU: Generic Reconfigurable Activation Unit Design for Neural Network Hardware Accelerators
Yuhao Liu, Salim Ullah, Akash Kumar
With the continuous growth of neural network scales, low-precision quantization is widely used in edge accelerators. Classic multi-threshold activation hardware requires 2^n thresh…