7 citations · 10 across the 7 of their papers we have counts for
8 papers
FlexRC: A Flexible Multi-Point Model Order Reduction Method for Many-Port RC Networks
Yuncheng Xu, Siyuan Yin, Lin Liu +4
Efficient model order reduction for many-port resistor-capacitor (RC) networks is essential in post-layout circuit simulation. Existing high-accuracy elimination-based methods have…
LLM-Assisted Op-Amp Behavioral-Level Design via Agentic Human-Mimicking Reasoning
Zihao Chen, Ziyi Sun, Jiayin Wang +6
This paper proposes White-Op, an operational amplifier (op-amp) behavioral-level parameter design framework assisted by the human-mimicking reasoning of large language model agents…
SMP-RCR: A Sparse Multipoint Moment Matching Method for RC Reduction
Siyuan Yin, Yuncheng Xu, Lin Liu +4
In post--layout circuit simulation, efficient model order reduction (MOR) for many--port resistor--capacitor (RC) circuits remains a crucial issue. The current mainstream MOR metho…
Dataset Construction for Training LLM to Learn Analog Circuit Knowledge
Zihao Chen, Ji Zhuang, Jinyi Shen +11
This paper constructs a textual dataset for training large language models (LLMs) to learn analog circuit knowledge and customizes LLM training techniques. For dataset construction…
The Power of Graph Signal Processing for Chip Placement Acceleration
Yiting Liu, Hai Zhou, Jia Wang +3
Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task,…
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis
Jintao Li, Haochang Zhi, Ruiyu Lyu +9
Recent advances in machine learning (ML) for automating analog circuit synthesis have been significant, yet challenges remain. A critical gap is the lack of a standardized evaluati…
Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement
Hongyang Pan, Cunqing Lan, Yiting Liu +5
A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages…
A Semi-Tensor Product based Circuit Simulation for SAT-sweeping
Hongyang Pan, Ruibing Zhang, Yinshui Xia +4
In recent years, circuit simulators and Boolean satisfiability (SAT) solvers have been tightly integrated to provide efficient logic synthesis and verification. Circuit simulation…