4 papers
PEEK: Heterogeneous Parallelism for Privileged Error Detection in Safety-Critical Processors
Tinglue Wang, Zhenghui Guo, Bing Guo +7
Heterogeneous parallel error detection architecture has been widely studied for safeguarding OoO superscalar processors in safetycritical systems, as it achieves significantly lowe…
CIM-Tuner: Balancing the Compute and Storage Capacity of SRAM-CIM Accelerator via Hardware-mapping Co-exploration
Jinwu Chen, Yuhui Shi, He Wang +4
As an emerging type of AI computing accelerator, SRAM Computing-In-Memory (CIM) accelerators feature high energy efficiency and throughput. However, various CIM designs and under-e…
cuPilot: A Strategy-Coordinated Multi-agent Framework for CUDA Kernel Evolution
Jinwu Chen, Qidie Wu, Bin Li +5
Optimizing CUDA kernels is a challenging and labor-intensive task, given the need for hardware-software co-design expertise and the proprietary nature of high-performance kernel li…
Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness
Zhe Jiang, Shuai Zhao, Ran Wei +3
In safety-critical systems, timing accuracy is the key to achieving precise I/O control. To meet such strict timing requirements, dedicated hardware assistance has recently been in…