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cs.AR2025
MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors
Dean You, Jieyu Jiang, Xiaoxuan Wang +9
Runahead execution is a technique to mask memory latency caused by irregular memory accesses. By pre-executing the application code during occurrences of long-latency operations an…
cs.AR2024
Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness
Zhe Jiang, Shuai Zhao, Ran Wei +3
In safety-critical systems, timing accuracy is the key to achieving precise I/O control. To meet such strict timing requirements, dedicated hardware assistance has recently been in…