1 citations · 1 across the 11 of their papers we have counts for
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Towards Understanding, Analyzing, and Optimizing Agentic AI Execution: A CPU-Centric Perspective
Ritik Raj, Souvik Kundu, Ishita Vohra +2
Agentic AI serving converts monolithic LLM-based inference to autonomous problem-solvers that can plan, call tools, perform reasoning, and adapt on the fly. Due to diverse task exe…
SCALE-Sim v3: A modular cycle-accurate systolic accelerator simulator for end-to-end system analysis
Ritik Raj, Sarbartha Banerjee, Nikhil Chandra +4
The rapid advancements in AI, scientific computing, and high-performance computing (HPC) have driven the need for versatile and efficient hardware accelerators. Existing tools like…
MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules
Ritik Raj, Shengjie Lin, William Won +1
Increasing AI computing demands and slowing transistor scaling have led to the advent of Multi-Chip-Module (MCMs) based accelerators. MCMs enable cost-effective scalability, higher…
OneDSE: Metric-Conditioned Inverse Modeling and Active Search for Sample-Efficient DSE
Ritik Raj, Akshat Ramachandran, Danny Samuel +3
We identify two key challenges in prior CPU design space exploration (DSE) approaches: (a) short-horizon prediction is forward-only: modeling PPA metrics from design parameters whi…
NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI
Hanchen Yang, Zishen Wan, Ritik Raj +5
Neuro-Symbolic AI (NSAI) is an emerging paradigm that integrates neural networks with symbolic reasoning to enhance the transparency, reasoning capabilities, and data efficiency of…
CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design
Zishen Wan, Hanchen Yang, Ritik Raj +4
Neurosymbolic AI is an emerging compositional paradigm that fuses neural learning with symbolic reasoning to enhance the transparency, interpretability, and trustworthiness of AI.…
Axon: A novel systolic array architecture for improved run time and energy efficient GeMM and Conv operation with on-chip im2col
Md Mizanur Rahaman Nayan, Ritik Raj, Gouse Basha Shaik +2
General matrix multiplication (GeMM) is a core operation in virtually all AI applications. Systolic array (SA) based architectures have shown great promise as GeMM hardware acceler…