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cs.AR2025
FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design
Mahmoud Nazzal, Khoa Nguyen, Deepak Vungarala +4
AI hardware design is advancing rapidly, driven by the promise of design automation to make chip development faster, more efficient, and more accessible to a wide range of users. A…
cs.AR2024
SA-DS: A Dataset for Large Language Model-Driven AI Accelerator Design Generation
Deepak Vungarala, Mahmoud Nazzal, Mehrdad Morsali +4
In the ever-evolving landscape of Deep Neural Networks (DNN) hardware acceleration, unlocking the true potential of systolic array accelerators has long been hindered by the daunti…