83 citations · 85 across the 10 of their papers we have counts for
10 papers
A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
Po-Chuan Wang, Dongwon Jang, Eknath Sarkar +5
We propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects…
ACRONYM: Accelerated Approximate Nearest Neighbor Search in Memory for Dynamic Vector Databases
Md Mizanur Rahaman Nayan, Tianqi Zhang, Flavio Ponzina +2
Vector database search with frequent updates is increasingly critical in applications such as retrieval augmented generation, recommendation systems, and large-scale embedding retr…
Modeling and Optimization of Two-Terminal Spin-Orbit-Torque MRAM
Md Nahid Haque Shazon, Piyush Kumar, Luqiao Liu +2
This paper presents physical modeling and benchmarking for two-terminal spin-orbit torque magnetic random-access memory (2T-SOT-MRAM). The results indicate that the common SOT mate…
Cross-Layer Co-Designed In-Memory Hyperdimensional Computing Accelerator for Proteomics at the Edge
Md Mizanur Rahaman Nayan, Zheyu Li, Flavio Ponzina +4
Database (DB) search and clustering are fundamental to data-analytics workloads such as mass spectrometry-driven proteomics. Current workflows rely on resource-intensive search and…
Content Addressable Memory Design with Reference Resistor for Improved Search Resolution
Siri Narla, Steven J. Koester, Rebecca A. Dawley +3
Despite the parallel in-memory search capabilities of content addressable memories (CAMs), their use in applications is constrained by their limited resolution that worsens as they…
HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional Computing
Md Mizanur Rahaman Nayan, Che-Kai Liu, Zishen Wan +2
Hyperdimensional computing (HDC) is a brain-inspired paradigm valued for its noise robustness, parallelism, energy efficiency, and low computational overhead. Hardware accelerators…
Axon: A novel systolic array architecture for improved run time and energy efficient GeMM and Conv operation with on-chip im2col
Md Mizanur Rahaman Nayan, Ritik Raj, Gouse Basha Shaik +2
General matrix multiplication (GeMM) is a core operation in virtually all AI applications. Systolic array (SA) based architectures have shown great promise as GeMM hardware acceler…
A 5T-2MTJ STT-assisted Spin Orbit Torque based Ternary Content Addressable Memory for Hardware Accelerators
Siri Narla, Piyush Kumar, Azad Naeemi
In this work, we present a novel non-volatile spin transfer torque (STT) assisted spin-orbit torque (SOT) based ternary content addressable memory (TCAM) with 5 transistors and 2 m…
Cross-layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search
Siri Narla, Piyush Kumar, Mohammad Adnaan +1
In this paper we present a comprehensive design and benchmarking study of Content Addressable Memory (CAM) at the 7nm technology node in the context of similarity search applicatio…
Roadmap for Unconventional Computing with Nanotechnology
Giovanni Finocchio, Jean Anne C. Incorvia, Joseph S. Friedman +48
In the "Beyond Moore's Law" era, with increasing edge intelligence, domain-specific computing embracing unconventional approaches will become increasingly prevalent. At the same ti…