2 citations · 12 across the 18 of their papers we have counts for
20 papers
Evidence-Guided Repository-Level RTL Repair
Yuxin Du, Juxin Niu, Zhe Jiang +1
Repository-level RTL repair must localize a failure that spans files, modules, and clock cycles, then propagate the fix consistently. Existing methods reason over source code, whic…
SeqFeed: Improving Agentic RTL Code Generation with Sequential Behavior Feedback
Yuxin Du, Juxin Niu, Tao Hu +3
RTL code generation is a critical stage in hardware design, and the emergence of agentic systems offers new opportunities to automate this process. To generate correct RTL code, ag…
ZK-Tracer: A High-Performance Heterogeneous Accelerator for Zero-Knowledge VM Trace Generation
Jieran Cui, Zhengkai Wen, Haowen Fang +6
Zero-knowledge virtual machines (zkVMs) are a key technology for driving the large-scale adoption of zero-knowledge proofs (ZKP), but their performance bottlenecks severely limit t…
UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
Junhao Ye, Dingrong Pan, Hanyuan Liu +7
Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of total effort. While the Universal Verification Methodology (UVM) improves r…
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
Lik Tung Fu, Jie Zhou, Shaokai Ren +6
Functional verification consumes over 50% of the IC development lifecycle, where SystemVerilog Assertions (SVAs) are indispensable for formal property verification and enhanced sim…
ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications
Changwen Xing, SamZaak Wong, Xinlai Wan +9
While Large Language Models (LLMs) demonstrate immense potential for automating integrated circuit (IC) development, their practical deployment is fundamentally limited by restrict…
ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
Jialin Sun, Yuchen Hu, Dean You +6
Functional verification is a critical bottleneck in integrated circuit development, with CPU verification being especially time-intensive and labour-consuming. Industrial practice…
VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs
Juxin Niu, Yuxin Du, Dan Niu +3
We present VerilogMonkey, an empirical study of parallel scaling for the under-explored task of automated Verilog generation. Parallel scaling improves LLM performance by sampling…
Re-thinking Memory-Bound Limitations in CGRAs
Xiangfeng Liu, Zhe Jiang, Anzhen Zhu +4
Coarse-Grained Reconfigurable Arrays (CGRAs) are specialized accelerators commonly employed to boost performance in workloads with iterative structures. Existing research typically…
ARSP: Automated Repair of Verilog Designs via Semantic Partitioning
Bingkun Yao, Ning Wang, Xiangfeng Liu +5
Debugging functional Verilog bugs consumes a significant portion of front-end design time. While Large Language Models (LLMs) have demonstrated great potential in mitigating this e…
FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification
Gwok-Waa Wan, Shengchu Su, Ruihu Wang +15
Despite the transformative potential of Large Language Models (LLMs) in hardware design, a comprehensive evaluation of their capabilities in design verification remains underexplor…
ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Juxin Niu, Xiangfeng Liu, Dan Niu +3
Coding with hardware description languages (HDLs) such as Verilog is a time-intensive and laborious task. With the rapid advancement of large language models (LLMs), there is incre…
VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
Ning Wang, Bingkun Yao, Jie Zhou +4
Large Language Models (LLMs) have demonstrated remarkable potential in debugging for various programming languages. However, the application of LLMs to Verilog debugging remains in…
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
Ning Wang, Bingkun Yao, Jie Zhou +4
Large language models (LLMs) have shown strong performance in Verilog generation from natural language description. However, ensuring the functional correctness of the generated co…
Exploiting the Uncertainty of the Longest Paths: Response Time Analysis for Probabilistic DAG Tasks
Yiyang Gao, Shuai Zhao, Boyang Li +4
Parallel real-time systems (e.g., autonomous driving systems) often contain functionalities with complex dependencies and execution uncertainties, leading to significant timing var…
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
Junhao Ye, Yuchen Hu, Ke Xu +8
Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of the total development effort. While the Universal Verification Methodology…
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Jie Zhou, Youshu Ji, Ning Wang +7
SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours…
UVLLM: An Automated Universal RTL Verification Framework using LLMs
Yuchen Hu, Junhao Ye, Ke Xu +11
Verifying hardware designs in embedded systems is crucial but often labor-intensive and time-consuming. While existing solutions have improved automation, they frequently rely on u…
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
Bingkun Yao, Ning Wang, Jie Zhou +4
Bug localization in Verilog code is a crucial and time-consuming task during the verification of hardware design. Since introduction, Large Language Models (LLMs) have showed their…
Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
Ning Wang, Bingkun Yao, Jie Zhou +3
Recent advancements in large language models (LLMs) have sparked significant interest in the automatic generation of Register Transfer Level (RTL) designs, particularly using Veril…