most citedLocation is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog

2 citations · 7 across the 7 of their papers we have counts for

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cs.AI2025

ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications

Changwen Xing, SamZaak Wong, Xinlai Wan +9

While Large Language Models (LLMs) demonstrate immense potential for automating integrated circuit (IC) development, their practical deployment is fundamentally limited by restrict…

cs.AI2025

ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection

Juxin Niu, Xiangfeng Liu, Dan Niu +3

Coding with hardware description languages (HDLs) such as Verilog is a time-intensive and laborious task. With the rapid advancement of large language models (LLMs), there is incre…