5 papers
Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core
Benjamin Hubinet, Pierre-Alain Moellic, Olivier Savry +2
By leveraging standard RISC-V extensions, namely Zfh (scalar float16) and Zvfh (vector float16), this work proposes an open-source framework to enable complete on-device training o…
Model Poisoning Against Federated Model Adaptation with Chain of Bit-Flips
Bastien Vuillod, Kevin Hector, Pierre-Alain Moellic +2
Federated Learning (FL) allows a set of clients to collectively train a global model without sharing local training data. Giving the responsibility of the training to decentralized…
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
Riccardo Tedeschi, Gianmarco Ottavi, Côme Allart +11
Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on t…
Using a Performance Model to Implement a Superscalar CVA6
Côme Allart, Jean-Roch Coulon, André Sintzoff +2
A performance model of CVA6 RISC-V processor is built to evaluate performance related modifications before implementing them in RTL. Its accuracy is 99.2% on CoreMark. This model i…
Fault Injection on Embedded Neural Networks: Impact of a Single Instruction Skip
Clement Gaine, Pierre-Alain Moellic, Olivier Potin +1
With the large-scale integration and use of neural network models, especially in critical embedded systems, their security assessment to guarantee their reliability is becoming an…