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20232026
most citedCorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design

4 citations · 18 across the 25 of their papers we have counts for

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Showing 2025Show all

7 papers · 1 filter

cs.AI2025

CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference

Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann +1

Large Language Models (LLMs) have demonstrated remarkable potential in hardware front-end design using hardware description languages (HDLs). However, their inherent tendency towar…

cs.AR2025

VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning

Zhuorui Zhao, Bing Li, Grace Li Zhang +1

Large Language Models (LLMs) have shown impressive potential in generating Verilog codes, but ensuring functional correctness remains a challenge. Existing approaches often rely on…

eess.SY2025

Large Language Models (LLMs) for Electronic Design Automation (EDA)

Kangwei Xu, Denis Schwachhofer, Jason Blocklove +10

With the growing complexity of modern integrated circuits, hardware engineers are required to devote more effort to the full design-to-manufacturing workflow. This workflow involve…

cs.CL2025

CompressKV: Semantic Retrieval Heads Know What Tokens are Not Important Before Generation

Xiaolin Lin, Jingcun Wang, Olga Kondrateva +3

Recent advances in large language models (LLMs) have significantly boosted long-context processing. However, the increasing key-value (KV) cache size poses critical challenges to m…

cs.SE2025★ 1 cited

HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis

Kangwei Xu, Bing Li, Grace Li Zhang +1

In high-level synthesis (HLS), C/C++ programs with synthesis directives are used to generate circuits for FPGA implementations. However, hardware-specific and platform-dependent ch…

cs.AR2025★ 1 cited

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency

Zhuorui Zhao, Ruidi Qiu, Ing-Chao Lin +3

Large Language Models (LLMs) have demonstrated promising capabilities in generating Verilog code from module specifications. To improve the quality of such generated Verilog codes,…

cs.PL2025★ 1 cited

Paradigm-Based Automatic HDL Code Generation Using LLMs

Wenhao Sun, Bing Li, Grace Li Zhang +3

While large language models (LLMs) have demonstrated the ability to generate hardware description language (HDL) code for digital circuits, they still face the hallucination proble…