6 papers
VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation
Yan Tan, Tong Liu, Xiangchen Meng +1
Large Language Models (LLMs) have recently achieved strong performance in software code generation. However, applying them to hardware description languages (HDLs), such as Verilog…
CellE: Automated Standard Cell Library Extension via Equality Saturation
Yi Ren, Yukun Wang, Xiang Meng +6
Automated standard cell library extension is crucial for maximizing Quality of Results (QoR) in modern VLSI design. We introduce CellE, a novel framework that leverages formal meth…
AutoVeriFix+: High-Correctness RTL Generation via Trace-Aware Causal Fix and Semantic Redundancy Pruning
Yan Tan, Xiangchen Meng, Zijun Jiang +1
Large language models (LLMs) have demonstrated impressive capabilities in generating software code for high-level programming languages such as Python and C++. However, their appli…
FedBit: Accelerating Privacy-Preserving Federated Learning via Bit-Interleaved Packing and Cross-Layer Co-Design
Xiangchen Meng, Yangdi Lyu
Federated learning (FL) with fully homomorphic encryption (FHE) effectively safeguards data privacy during model aggregation by encrypting local model updates before transmission,…
AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code
Yan Tan, Xiangchen Meng, Zijun Jiang +1
Large language models (LLMs) have demonstrated impressive capabilities in generating software code for high-level programming languages such as Python and C++. However, their appli…
HF-NTT: Hazard-Free Dataflow Accelerator for Number Theoretic Transform
Xiangchen Meng, Zijun Jiang, Yangdi Lyu
Polynomial multiplication is one of the fundamental operations in many applications, such as fully homomorphic encryption (FHE). However, the computational inefficiency stemming fr…