most citedVHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation

1 citations · 1 across the 2 of their papers we have counts for

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2 papers

cs.LG2024

CIRCUITSYNTH: Leveraging Large Language Models for Circuit Topology Synthesis

Prashanth Vijayaraghavan, Luyao Shi, Ehsan Degan +1

Circuit topology generation plays a crucial role in the design of electronic circuits, influencing the fundamental functionality of the circuit. In this paper, we introduce CIRCUIT…

cs.SE2024★ 1 cited

VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation

Prashanth Vijayaraghavan, Luyao Shi, Stefano Ambrogio +4

With the unprecedented advancements in Large Language Models (LLMs), their application domains have expanded to include code generation tasks across various programming languages.…