12 citations · 12 across the 6 of their papers we have counts for
6 papers
Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware
Jianan Mu, Mingyu Shi, Yining Wang +5
LLM-based RTL generation is an interesting research direction, as it holds the potential to liberate the least automated stage in the current chip design. However, due to the subst…
FicGCN: Unveiling the Homomorphic Encryption Efficiency from Irregular Graph Convolutional Networks
Zhaoxuan Kan, Husheng Han, Shangyi Shi +5
Graph Convolutional Neural Networks (GCNs) have gained widespread popularity in various fields like personal healthcare and financial systems, due to their remarkable performance.…
Extend IVerilog to Support Batch RTL Fault Simulation
Jiaping Tang, Jianan Mu, Zizhen Liu +3
The advancement of functional safety has made RTL-level fault simulation increasingly important to achieve iterative efficiency in the early stages of design and to ensure complian…
ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy
Jiaping Tang, Jianan Mu, Silin Liu +8
As intelligent computing devices increasingly integrate into human life, ensuring the functional safety of the corresponding electronic chips becomes more critical. A key metric fo…
FlexMem: High-Parallel Near-Memory Architecture for Flexible Dataflow in Fully Homomorphic Encryption
Shangyi Shi, Husheng Han, Jianan Mu +7
Fully Homomorphic Encryption (FHE) imposes substantial memory bandwidth demands, presenting significant challenges for efficient hardware acceleration. Near-memory Processing (NMP)…
TensorTEE: Unifying Heterogeneous TEE Granularity for Efficient Secure Collaborative Tensor Computing
Husheng Han, Xinyao Zheng, Yuanbo Wen +11
Heterogeneous collaborative computing with NPU and CPU has received widespread attention due to its substantial performance benefits. To ensure data confidentiality and integrity d…