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cs.AR2026
VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation
Luca Collini, Andrew Hennesee, Patrick Yubeaton +2
Rapid advances in language models (LMs) have created new opportunities for automated code generation while complicating trade-offs between model characteristics and prompt design c…
cs.AR2026
Exploring the Agentic Frontier of Verilog Code Generation
Patrick Yubeaton, Siddharth Garg, Chinmay Hegde
Large language models (LLMs) have made rapid advancements in code generation for popular languages such as Python and C++. Many of these recent gains can be attributed to the use o…