3 papers
cs.AR2024
Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems
Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi +1
The design space exploration of scaled-out manycores for communication-intensive applications (e.g., graph analytics and sparse linear algebra) is hampered due to either lack of sc…
cs.AR2024
Tascade: Hardware Support for Atomic-free, Asynchronous and Efficient Reduction Trees
Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff +1
Graph search and sparse data-structure traversal workloads contain challenging irregular memory patterns on global data structures that need to be modified atomically. Distributed…
cs.AR2024
DCRA: A Distributed Chiplet-based Reconfigurable Architecture for Irregular Applications
Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi +1
In recent years, the growing demand to process large graphs and sparse datasets has led to increased research efforts to develop hardware- and software-based architectural solution…