activity
20242026
most citedLogistic Map Pseudo Random Number Generator in FPGA

12 citations · 19 across the 8 of their papers we have counts for

collaborators

9 papers

cs.LG2026

GoQuant: Geometric Orthogonal Residual Projection for Multiplier-Free Power-of-Two Transformer Quantization

Maoyang Xiang, Tao Luo, Bo Wang

The deployment of Large Language Models (LLMs) and Vision Transformers (ViTs) on edge devices is significantly constrained by memory capacity and the critical timing bottlenecks in…

cs.LG2026

DAPA: Distribution Aware Piecewise Activation Functions for On-Device Transformer Inference and Training

Maoyang Xiang, Bo Wang

Non-linear activation functions play a pivotal role in on-device inference and training, as they not only consume substantial hardware resources but also impose a significant impac…

cs.AR2025

On-Device Qwen2.5: Efficient LLM Inference with Model Compression and Hardware Acceleration

Maoyang Xiang, Ramesh Fernando, Bo Wang

Transformer-based Large Language Models (LLMs) have significantly advanced AI capabilities but pose considerable challenges for deployment on edge devices due to high computational…

cs.CY2024

How to Mitigate the Dependencies of ChatGPT-4o in Engineering Education

Maoyang Xiang, T. Hui Teo

The rapid evolution of large multimodal models (LMMs) has significantly impacted modern teaching and learning, especially in computer engineering. While LMMs offer extensive opport…

cs.CR2024★ 3 cited

FPGA Digital Dice using Pseudo Random Number Generator

Michael Lim Kee Hian, Ten Wei Lin, Zachary Wu Xuan +3

The goal of this project is to design a digital dice that displays dice numbers in real-time. The number is generated by a pseudo-random number generator (PRNG) using XORshift algo…

cs.CR2024★ 12 cited

Logistic Map Pseudo Random Number Generator in FPGA

Mateo Jalen Andrew Calderon, Lee Jun Lei Lucas, Syarifuddin Azhar Bin Rosli +4

This project develops a pseudo-random number generator (PRNG) using the logistic map, implemented in Verilog HDL on an FPGA and processes its output through a Central Limit Theorem…

cs.AR2024★ 3 cited

Digital ASIC Design with Ongoing LLMs: Strategies and Prospects

Maoyang Xiang, Emil Goh, T. Hui Teo

The escalating complexity of modern digital systems has imposed significant challenges on integrated circuit (IC) design, necessitating tools that can simplify the IC design flow.…

cs.CR2024★ 1 cited

Hardware Implementation of Double Pendulum Pseudo Random Number Generator

Jarrod Lim, Tom Manuel Opalla Piccio, Chua Min Jie Michelle +2

The objective of this project is to utilize an FPGA board which is the CMOD A7 35t to obtain a pseudo random number which can be used for encryption. We aim to achieve this by leve…

cs.AR2024

From English to ASIC: Hardware Implementation with Large Language Model

Emil Goh, Maoyang Xiang, I-Chyn Wey +1

In the realm of ASIC engineering, the landscape has been significantly reshaped by the rapid development of LLM, paralleled by an increase in the complexity of modern digital circu…