78 citations · 225 across the 19 of their papers we have counts for
20 papers · 1 filter
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti +20
Next-generation mixed-criticality Systems-on-chip (SoCs) for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ens…
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET
Paul Scheffler, Thomas Benz, Viviane Potocnik +12
ML and HPC applications increasingly combine dense and sparse memory access computations to maximize storage efficiency. However, existing CPUs and GPUs struggle to flexibly handle…
Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads
Matteo Perotti, Michele Raeber, Mattia Sinigaglia +3
Multi-core vector processor architectures excel in handling computationally intensive vectorizable tasks but struggle to achieve optimal resource utilization when facing sequential…
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET
Gianna Paulin, Paul Scheffler, Thomas Benz +11
We present Occamy, a 432-core RISC-V dual-chiplet 2.5D system for efficient sparse linear algebra and stencil computations on FP64 and narrow (32-, 16-, 8-bit) SIMD FP data. Occamy…
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication
Matteo Perotti, Yichao Zhang, Matheus Cavalcante +2
Dense Matrix Multiplication (MatMul) is arguably one of the most ubiquitous compute-intensive kernels, spanning linear algebra, DSP, graphics, and machine learning applications. Th…
Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV 1.0 Compliant Open-Source Processor
Matteo Perotti, Matheus Cavalcante, Renzo Andri +2
Vector processing is highly effective in boosting processor performance and efficiency for data-parallel workloads. In this paper, we present Ara2, the first fully open-source vect…
Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency
Matteo Perotti, Samuel Riedel, Matheus Cavalcante +1
The ever-increasing computational and storage requirements of modern applications and the slowdown of technology scaling pose major challenges to designing and implementing efficie…
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge
Vikram Jain, Matheus Cavalcante, Nazareno Bruschi +6
Emerging deep neural network (DNN) applications require high-performance multi-core hardware acceleration with large data bursts. Classical network-on-chips (NoCs) use serial packe…
FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic
Tim Fischer, Michael Rogenmoser, Matheus Cavalcante +2
Meeting the staggering bandwidth requirements of today's applications challenges the traditional narrow and serialized NoCs, which hit hard bounds on the maximum operating frequenc…
MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory
Samuel Riedel, Matheus Cavalcante, Renzo Andri +1
Shared L1 memory clusters are a common architectural pattern (e.g., in GPGPUs) for building efficient and flexible multi-processing-element (PE) engines. However, it is a common be…
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference
MohammadHossein AskariHemmat, Theo Dupuis, Yoan Fournier +8
In this paper, we present Quark, an integer RISC-V vector processor specifically tailored for sub-byte DNN inference. Quark is implemented in GlobalFoundries' 22FDX FD-SOI technolo…
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement
Patrick Iff, Maciej Besta, Matheus Cavalcante +3
2.5D integration is an important technique to tackle the growing cost of manufacturing chips in advanced technology nodes. This poses the challenge of providing high-performance in…
Sparse Hamming Graph: A Customizable Network-on-Chip Topology
Patrick Iff, Maciej Besta, Matheus Cavalcante +3
Chips with hundreds to thousands of cores require scalable networks-on-chip (NoCs). Customization of the NoC topology is necessary to reach the diverse design goals of different ch…
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
Matteo Perotti, Matheus Cavalcante, Nils Wistoff +3
Vector architectures are gaining traction for highly efficient processing of data-parallel workloads, driven by all major ISAs (RISC-V, Arm, Intel), and boosted by landmark chips,…
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters
Gianna Paulin, Matheus Cavalcante, Paul Scheffler +4
Modern high-performance computing architectures (Multicore, GPU, Manycore) are based on tightly-coupled clusters of processing elements, physically implemented as rectangular tiles…
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters
Matheus Cavalcante, Domenic Wüthrich, Matteo Perotti +2
While parallel architectures based on clusters of Processing Elements (PEs) sharing L1 memory are widespread, there is no consensus on how lean their PE should be. Architecting PEs…
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration
Matheus Cavalcante, Anthony Agnesina, Samuel Riedel +6
Three-dimensional integrated circuits promise power, performance, and footprint gains compared to their 2D counterparts, thanks to drastic reductions in the interconnects' length t…
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect
Matheus Cavalcante, Samuel Riedel, Antonio Pullini +1
A key challenge in scaling shared-L1 multi-core clusters towards many-core (more than 16 cores) configurations is to ensure low-latency and efficient access to the L1 memory. In th…
An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication
Andreas Kurth, Wolfgang Rönninger, Thomas Benz +4
On-chip communication infrastructure is a central component of modern systems-on-chip (SoCs), and it continues to gain importance as the number of cores, the heterogeneity of compo…
Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI
Matheus Cavalcante, Fabian Schuiki, Florian Zaruba +2
In this paper, we present Ara, a 64-bit vector processor based on the version 0.5 draft of RISC-V's vector extension, implemented in GlobalFoundries 22FDX FD-SOI technology. Ara's…