18 papers
Assessing Triple Modular Redundancy for Wide-Link, Low-Latency NoC Routers: Reliability and Physical Design Challenges
Chen Wu, Michael Rogenmoser, Luca Benini +1
Protecting the Network-on-Chip (NoC) of physical-AI tile-based accelerators deployed in harsh environments against single-event effects (SEEs) is paramount for preventing NoC failu…
CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems
Enrico Zelioli, Christopher Reinwardt, Nils Wistoff +4
This work presents CVA6-RT, a real-time micro-architectural extension of the CVA6 core to bound worst-case latency and reduce task's timing execution variability. CVA6-RT implement…
Not All Faults Are Equal: Transient-Fault Sensitivity Characterization of an Open-Source RISC-V Vector Cluster
Maoyuan Cai, Amirhossein Kiamarzi, Davide Rossi +1
We present a transient-fault sensitivity study of the open-source RISC-V vector cluster Spatz under SET and SEU fault models. Across 100,000 fault injections on six MatMul and Wide…
Who Checks the Checker? Enhancing Component-level Architectural SEU Fault Tolerance for End-to-End SoC Protection
Michael Rogenmoser, Philippe Sauter, Chen Wu +2
Single-event upset (SEU) fault tolerance for systems-on-chip (SoCs) in radiation-heavy environments is often addressed by architectural fault-tolerance approaches protecting indivi…
VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration
Max Wipfli, Gamze Ä°slamoÄlu, Navaneeth Kunhi Purayil +2
Compared to the first generation of deep neural networks, dominated by regular, compute-intensive kernels such as matrix multiplications (MatMuls) and convolutions, modern decoder-…
relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
Michael Rogenmoser, Angelo Garofalo, Luca Benini
On-chip communication is a critical element of modern systems-on-chip (SoCs), allowing processor cores to interact with memory and peripherals. Interconnects require special care i…