3 papers
cs.LG2024
The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation
Reza Moravej, Saurabh Bodhe, Zhanguang Zhang +6
Logic synthesis is a crucial phase in the circuit design process, responsible for transforming hardware description language (HDL) designs into optimized netlists. However, traditi…
cs.LG2024
Scalable Graph Self-Supervised Learning
Ali Saheb Pasand, Reza Moravej, Mahdi Biparva +2
In regularization Self-Supervised Learning (SSL) methods for graphs, computational complexity increases with the number of nodes in graphs and embedding dimensions. To mitigate the…
cs.LG2024
WERank: Towards Rank Degradation Prevention for Self-Supervised Learning Using Weight Regularization
Ali Saheb Pasand, Reza Moravej, Mahdi Biparva +1
A common phenomena confining the representation quality in Self-Supervised Learning (SSL) is dimensional collapse (also known as rank degeneration), where the learned representatio…