4 papers
STT-RAM-based Hierarchical In-Memory Computing
Dhruv Gajaria, Kevin Antony Gomez, Tosiron Adegbija
In-memory computing promises to overcome the von Neumann bottleneck in computer systems by performing computations directly within the memory. Previous research has suggested using…
CHIME: Energy-Efficient STT-RAM-based Concurrent Hierarchical In-Memory Processing
Dhruv Gajaria, Tosiron Adegbija, Kevin Gomez
Processing-in-cache (PiC) and Processing-in-memory (PiM) architectures, especially those utilizing bit-line computing, offer promising solutions to mitigate data movement bottlenec…
ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors
Dhruv Gajaria, Tosiron Adegbija
Relaxed retention (or volatile) spin-transfer torque RAM (STT-RAM) has been widely studied as a way to reduce STT-RAM's write energy and latency overheads. Given a relaxed retentio…
SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning
Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija
Prior studies have shown that the retention time of the non-volatile spin-transfer torque RAM (STT-RAM) can be relaxed in order to reduce STT-RAM's write energy and latency. Howeve…