3 papers
cs.AR2026
SegFold: Accelerating Sparse GEMM with a Fine-Grained Dynamic Dataflow
Xinrui Wu, Hanyu Wang, Jason Cong +1
Generalized sparse matrix-matrix multiplication (SpGEMM) is critical in many domains. Existing CPUs and GPUs, as well as specialized accelerators, rely on static dataflows (e.g., i…
cs.AR2025
FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs
Stefan Abi-Karam, Rishov Sarkar, Suhail Basalama +2
Dataflow hardware designs enable efficient FPGA implementations via high-level synthesis (HLS), but correctly sizing first-in-first-out (FIFO) channel buffers remains challenging.…
cs.AR2025
Demystifying FPGA Hard NoC Performance
Sihao Liu, Jake Ke, Tony Nowatzki +1
With the advent of modern multi-chiplet FPGA architectures, vendors have begun integrating hardened NoC to address the scalability, resource usage, and frequency disadvantages of s…