2 papers
cs.AR2024
Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer
Xiangfei Hu, Yuyang Ye, Tinghuan Chen +2
With the shrinking technology nodes, timing optimization becomes increasingly challenging. Approximate logic synthesis (ALS) can perform local approximate changes (LACs) on circuit…
cs.LG2024
Learning-driven Physically-aware Large-scale Circuit Gate Sizing
Yuyang Ye, Peng Xu, Lizheng Ren +4
Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths…