10 papers
ARMOR: Accelerating RTL Simulation by Mitigating the Front-End Bottleneck Using Node Compression
Jiaping Tang, Jianan Mu, Zhiteng Chao +3
RTL simulation is indispensable in chip design. High-performance simulators typically lower each node in the RTL graph into an instruction sequence. Although this per-node lowering…
Lifecycle Cost-Effectiveness Modeling for Redundancy-Enhanced Multi-Chiplet Architectures
Zizhen Liu, Fangzhiyi Wang, Mengdi Wang +4
The growing demand for compute-intensive applications has made multi-chiplet architectures a promising alternative to monolithic designs, offering improved scalability and manufact…
Analysis of LLM Vulnerability to GPU Soft Errors: An Instruction-Level Fault Injection Study
Duo Chai, Zizhen Liu, Shuhuai Wang +4
Large language models (LLMs) are highly compute- and memory-intensive, posing significant demands on high-performance GPUs. At the same time, advances in GPU technology driven by s…
ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction
Bin Sun, Jingyi Zhou, Jianan Mu +5
In traditional EDA flows, layout-level performance metrics are only obtainable after placement and routing, hindering global optimization at earlier stages. Although some neural-ne…
InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning
Bin Sun, Rengang Zhang, Zhiteng Chao +4
Automatic test pattern generation (ATPG) is a crucial process in integrated circuit (IC) design and testing, responsible for efficiently generating test patterns. As semiconductor…
Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT
Zhiteng Chao, Yonghao Wang, Xinyu Zhang +9
Large language models (LLMs) hold promise for automating integrated circuit (IC) engineering using register transfer level (RTL) hardware description languages (HDLs) like Verilog.…