5 papers
ARMOR: Accelerating RTL Simulation by Mitigating the Front-End Bottleneck Using Node Compression
Jiaping Tang, Jianan Mu, Zhiteng Chao +3
RTL simulation is indispensable in chip design. High-performance simulators typically lower each node in the RTL graph into an instruction sequence. Although this per-node lowering…
Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction
Jiaping Tang, Jianan Mu, Tianyun Ma +3
Debugging represents a time-consuming and labor-intensive task in hardware design, with bug localization constituting a substantial portion of this process. While spectrum-based bu…
RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule
Jiaping Tang, Jianan Mu, Zizhen Liu +6
With the rapid development of safety-critical applications such as autonomous driving and embodied intelligence, the functional safety of the corresponding electronic chips becomes…
Extend IVerilog to Support Batch RTL Fault Simulation
Jiaping Tang, Jianan Mu, Zizhen Liu +3
The advancement of functional safety has made RTL-level fault simulation increasingly important to achieve iterative efficiency in the early stages of design and to ensure complian…
ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy
Jiaping Tang, Jianan Mu, Silin Liu +8
As intelligent computing devices increasingly integrate into human life, ensuring the functional safety of the corresponding electronic chips becomes more critical. A key metric fo…