3 papers
cs.SE2026
Dockerless: Environment-Free Program Verifier for Coding Agents
Wenhao Zeng, Yuling Shi, Xiaodong Gu +10
Program verifiers play a central role in training coding agents, including selecting trajectories for supervised fine-tuning (SFT) and providing rewards for reinforcement learning…
cs.LG2025
VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning
Fu Teng, Miao Pan, Xuhong Zhang +6
Recent advancements in code generation have shown remarkable success across software domains, yet hardware description languages (HDLs) such as Verilog remain underexplored due to…
cs.PL2025
HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers
Yiyao Yang, Fu Teng, Pengju Liu +5
Recently, the use of large language models (LLMs) for Verilog code generation has attracted great research interest to enable hardware design automation. However, previous works ha…