13 citations · 18 across the 4 of their papers we have counts for
4 papers
ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework
Qijun Zhang, Shang Liu, Yao Lu +2
Power is a primary objective in modern processor design, requiring accurate yet efficient power modeling techniques. Architecture-level power models are necessary for early power o…
AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
Qijun Zhang, Yao Lu, Mengming Li +1
Power efficiency is a critical design objective in modern CPU design. Architects need a fast yet accurate architecture-level power evaluation tool to perform early-stage power esti…
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
Wenji Fang, Yao Lu, Shang Liu +5
In modern VLSI design flow, the register-transfer level (RTL) stage is a critical point, where designers define precise design behavior with hardware description languages (HDLs) l…
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Yao Lu, Shang Liu, Qijun Zhang +1
Inspired by the recent success of large language models (LLMs) like ChatGPT, researchers start to explore the adoption of LLMs for agile hardware design, such as generating design…