1 citations · 1 across the 2 of their papers we have counts for
3 papers
cs.AR2026★ 1 cited
ChatModel: Automating Reference Model Design and Verification with LLMs
Jianmin Ye, Tianyang Liu, Qi Tian +3
As the complexity of integrated circuit designs continues to escalate, functional verification becomes increasingly challenging. Reference models, critical for accelerating the ver…
cs.SE2026
RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation
Yifan Zhang, Jianmin Ye, Jiahao Yang +1
As the complexity of System-on-Chip (SoC) designs grows, the shift-left paradigm necessitates the rapid development of high-fidelity reference models (typically written in SystemC)…
cs.AR2025
FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification
Gwok-Waa Wan, Shengchu Su, Ruihu Wang +15
Despite the transformative potential of Large Language Models (LLMs) in hardware design, a comprehensive evaluation of their capabilities in design verification remains underexplor…