1 citations · 1 across the 2 of their papers we have counts for
2 papers
cs.CV2026
SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes
Chia-Tung Ho, Haoyu Yang, Guanglei Zhou +6
As semiconductor manufacturing advances toward sub-2nm nodes, local place-and-route (P&R) design-rule violation (DRV) fixing is increasingly limited by complex rule interactions, d…
cs.AR2022★ 1 cited
TAG: Learning Circuit Spatial Embedding From Layouts
Keren Zhu, Hao Chen, Walker J. Turner +4
Analog and mixed-signal (AMS) circuit designs still rely on human design expertise. Machine learning has been assisting circuit design automation by replacing human experience with…