92 citations · 100 across the 15 of their papers we have counts for
5 papers · 1 filter
DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base
Zahin Ibnat, Paul E. Calzada, Rasin Mohammed Ihtemam +4
As large language models (LLMs) continue to be integrated into modern technology, there has been an increased push towards code generation applications, which also naturally extend…
SVAgent: AI Agent for Hardware Security Verification Assertion
Rui Guo, Avinash Ayalasomayajula, Henian Li +3
Verification using SystemVerilog assertions (SVA) is one of the most popular methods for detecting circuit design vulnerabilities. However, with the globalization of integrated cir…
VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation
Paul E. Calzada, Zahin Ibnat, Tanvir Rahman +5
Large Language Models (LLMs) are gaining popularity for hardware design automation, particularly through Register Transfer Level (RTL) code generation. In this work, we examine the…
SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
Dipayan Saha, Shams Tarek, Hasan Al Shaikh +8
Ensuring the security of complex system-on-chips (SoCs) designs is a critical imperative, yet traditional verification techniques struggle to keep pace due to significant challenge…
BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detection
Shams Tarek, Dipayan Saha, Sujan Kumar Saha +1
The current landscape of system-on-chips (SoCs) security verification faces challenges due to manual, labor-intensive, and inflexible methodologies. These issues limit the scalabil…