11 citations · 24 across the 18 of their papers we have counts for
19 papers
Scalable Attention for 5G NR Channel Estimation
Mahdi Abdollahpour, Marco Bertuletti, Yichao Zhang +2
Attention-based neural estimators achieve strong channel-estimation accuracy, but the computational cost of global attention over the time-frequency resource grid grows quadratical…
Accelerating Precise End-to-End Simulation: Latency-Sensitive Many-core System Modeling
Yinrong Li, Zexin Fu, Yichao Zhang +5
Modern large language model workloads put increasing demands on parallel compute capability and on-chip memory capacity, while also stressing fine-grained data movement and synchro…
TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks
Marco Bertuletti, Yichao Zhang, Diyou Shen +3
The upcoming integration of AI in the physical layer (PHY) of 6G radio access networks (RAN) will enable a higher quality of service in challenging transmission scenarios. However,…
TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link
Yichao Zhang, Marco Bertuletti, Chi Zhang +5
Shared L1-memory clusters of streamlined instruction processors (processing elements - PEs) are commonly used as building blocks in modern, massively parallel computing architectur…
A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN
Yichao Zhang, Marco Bertuletti, Sergio Mazzola +2
We present HeartStream, a 64-RV-core shared-L1-memory cluster (410 GFLOP/s peak performance and 204.8 GBps L1 bandwidth) for energy-efficient AI-enhanced O-RAN. The cores and clust…
A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks
Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli +1
Following the scale-up of new radio (NR) complexity in 5G and beyond, the physical layer's computing load on base stations is increasing under a strictly constrained latency and po…
Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access Networks
Marco Bertuletti, Yichao Zhang, Mahdi Abdollahpour +2
The fast-rising demand for wireless bandwidth requires rapid evolution of high-performance baseband processing infrastructure. Programmable many-core processors for software-define…
TeraNoC: A Multi-Channel 32-bit Fine-Grained, Hybrid Mesh-Crossbar NoC for Efficient Scale-up of 1000+ Core Shared-L1-Memory Clusters
Yichao Zhang, Zexin Fu, Tim Fischer +3
A key challenge in on-chip interconnect design is to scale up bandwidth while maintaining low latency and high area efficiency. 2D-meshes scale with low wiring area and congestion…
A Dynamic Allocation Scheme for Adaptive Shared-Memory Mapping on Kilo-core RV Clusters for Attention-Based Model Deployment
Bowen Wang, Marco Bertuletti, Yichao Zhang +2
Attention-based models demand flexible hardware to manage diverse kernels with varying arithmetic intensities and memory access patterns. Large clusters with shared L1 memory, a co…
A Compute&Memory Efficient Model-Driven Neural 5G Receiver for Edge AI-assisted RAN
Mahdi Abdollahpour, Marco Bertuletti, Yichao Zhang +3
Artificial intelligence approaches for base-band processing for radio receivers have demonstrated significant performance gains. Most of the proposed methods are characterized by h…
Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication
Samuel Riedel, Yichao Zhang, Marco Bertuletti +1
Next-generation wireless technologies (for immersive-massive communication, joint communication and sensing) demand highly parallel architectures for massive data processing. A com…
Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications
Danilo Cammarata, Matteo Perotti, Marco Bertuletti +4
The rapid growth of AI-based Internet-of-Things applications increased the demand for high-performance edge processing engines on a low-power budget and tight area constraints. As…
MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster
Sergio Mazzola, Yichao Zhang, Marco Bertuletti +2
As computational paradigms evolve, applications such as attention-based models, wireless telecommunications, and computer vision impose increasingly challenging requirements on com…
Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing
Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti +11
Most Wearable Ultrasound (WUS) devices lack the computational power to process signals at the edge, instead relying on remote offload, which introduces latency, high power consumpt…
TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs
Diyou Shen, Yichao Zhang, Marco Bertuletti +1
As computing demand and memory footprint of deep learning applications accelerate, clusters of cores sharing local (L1) multi-banked memory are widely used as key building blocks i…
A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR
Yichao Zhang, Marco Bertuletti, Chi Zhang +3
We introduce an open-source architecture for next-generation Radio-Access Network baseband processing: 1024 latency-tolerant 32-bit RISC-V cores share 4 MiB of L1 memory via an ult…
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios
Yichao Zhang, Marco Bertuletti, Samuel Riedel +3
Radio Access Networks (RAN) workloads are rapidly scaling up in data processing intensity and throughput as the 5G (and beyond) standards grow in number of antennas and sub-carrier…
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster
Marco Bertuletti, Samuel Riedel, Yichao Zhang +2
Synchronization is likely the most critical performance killer in shared-memory parallel programs. With the rise of multi-core and many-core processors, the relative impact on perf…
Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor
Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli +1
5G Radio access network disaggregation and softwarization pose challenges in terms of computational performance to the processing units. At the physical layer level, the baseband p…