28 citations · 66 across the 10 of their papers we have counts for
3 papers · 1 filter
Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Nathaniel Pinckney, Chenhui Deng, Chia-Tung Ho +5
We present the Comprehensive Verilog Design Problems (CVDP) benchmark, a new dataset and infrastructure to advance LLM and agent research in hardware design and verification. CVDP…
VerilogEval: Evaluating Large Language Models for Verilog Code Generation
Mingjie Liu, Nathaniel Pinckney, Brucek Khailany +1
The increasing popularity of large language models (LLMs) has paved the way for their application in diverse domains. This paper proposes a benchmarking framework tailored specific…
An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
Mingjie Liu, Haoyu Yang, Zongyi Li +7
Lithography modeling is a crucial problem in chip design to ensure a chip design mask is manufacturable. It requires rigorous simulations of optical and chemical models that are co…