2 papers
cs.AR2022
The AMD Rome Memory Barrier
Phillip Allen Lane, Jessica Lobrano
With the rapid growth of AMD as a competitor in the CPU industry, it is imperative that high-performance and architectural engineers analyze new AMD CPUs. By understanding new and…
cs.DC2022
Heterogeneous Sparse Matrix-Vector Multiplication via Compressed Sparse Row Format
Phillip Allen Lane, Joshua Dennis Booth
Sparse matrix-vector multiplication (SpMV) is one of the most important kernels in high-performance computing (HPC), yet SpMV normally suffers from ill performance on many devices.…