3 citations · 4 across the 11 of their papers we have counts for
11 papers
Mega: A 22 nm Convolutional Spiking Neural Network Accelerator Achieving 0.375 pJ/SOP for Efficient Edge Vision
Rick Luiken, Manil Dev Gomony, Sander Stuijk
Convolutional Spiking Neural Networks (SNN) offer the potential for highly energy-efficient vision processing by exploiting sparse, event-driven computation. However, existing SNN…
CIMple: Standard-cell SRAM-based CIM with LUT-based split softmax for attention acceleration
Bas Ahn, Xingjian Tao, Manil Dev Gomony +2
Large Language Models (LLMs) such as LLaMA and DeepSeek, are built on transformer architectures, which have become a standard model for achieving state-of-the-art performance in na…
LOREN: Low Rank-Based Code-Rate Adaptation in Neural Receivers
Bram Van Bolderik, Vlado Menkovski, Sonia Heemstra de Groot +1
Neural network based receivers have recently demonstrated superior system-level performance compared to traditional receivers. However, their practicality is limited by high memory…
LOKI: a 0.266 pJ/SOP Digital SNN Accelerator with Multi-Cycle Clock-Gated SRAM in 22nm
Rick Luiken, Lorenzo Pes, Manil Dev Gomony +1
Bio-inspired sensors like Dynamic Vision Sensors (DVS) and silicon cochleas are often combined with Spiking Neural Networks (SNNs), enabling efficient, event-driven processing simi…
Fibbinary-Based Compression and Quantization for Efficient Neural Radio Receivers
Roberta Fiandaca, Manil Dev Gomony
Neural receivers have shown outstanding performance compared to the conventional ones but this comes with a high network complexity leading to a heavy computational cost. This pose…
LinkBo: An Adaptive Single-Wire, Low-Latency, and Fault-Tolerant Communications Interface for Variable-Distance Chip-to-Chip Systems
Bochen Ye, Gustavo Naspolini, Kimmo Salo +1
Cost-effective embedded systems necessitate utilizing the single-wire communication protocol for inter-chip communication, thanks to its reduced pin count in comparison to the mult…
A Unified Framework for Mapping and Synthesis of Approximate R-Blocks CGRAs
Georgios Alexandris, Panagiotis Chaidos, Alexis Maras +5
The ever-increasing complexity and operational diversity of modern Neural Networks (NNs) have caused the need for low-power and, at the same time, high-performance edge devices for…
Efficient Synaptic Delay Implementation in Digital Event-Driven AI Accelerators
Roy Meijer, Paul Detterer, Amirreza Yousefzadeh +8
Synaptic delay parameterization of neural network models have remained largely unexplored but recent literature has been showing promising results, suggesting the delay parameteriz…
Hardware-aware training of models with synaptic delays for digital event-driven neuromorphic processors
Alberto Patino-Saucedo, Roy Meijer, Amirreza Yousefzadeh +6
Configurable synaptic delays are a basic feature in many neuromorphic neural network hardware accelerators. However, they have been rarely used in model implementations, despite th…
THOR -- A Neuromorphic Processor with 7.29G TSOP/mmJs Energy-Throughput Efficiency
Mayank Senapati, Manil Dev Gomony, Sherif Eissa +2
Neuromorphic computing using biologically inspired Spiking Neural Networks (SNNs) is a promising solution to meet Energy-Throughput (ET) efficiency needed for edge computing device…
BrainTTA: A 35 fJ/op Compiler Programmable Mixed-Precision Transport-Triggered NN SoC
Maarten Molendijk, Floran de Putter, Manil Gomony +2
Recently, accelerators for extremely quantized deep neural network (DNN) inference with operand widths as low as 1-bit have gained popularity due to their ability to largely cut do…