2 papers
cs.SE2026
SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Design
Jian Zuo, Junzhe Liu, Xianyong Wang +6
Recent advances in large language models (LLMs) have demonstrated strong potential in generating hardware designs using hardware description languages (HDLs) such as Verilog. Howev…
cs.SE2025
ClassEval-T: Evaluating Large Language Models in Class-Level Code Translation
Pengyu Xue, Linhao Wu, Zhen Yang +9
In recent years, Large Language Models (LLMs) have dramatically advanced the performance of automated code translation, making their computational accuracy score reach up to over 8…