2 papers
cs.SE2026
SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Design
Jian Zuo, Junzhe Liu, Xianyong Wang +6
Recent advances in large language models (LLMs) have demonstrated strong potential in generating hardware designs using hardware description languages (HDLs) such as Verilog. Howev…
cs.ET2026
CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval
Xinzhao Li, Alptekin Vardar, Franz Müller +6
Deploying Retrieval-Augmented Generation (RAG) on edge devices is in high demand, but is hindered by the latency of massive data movement and computation on traditional architectur…