23 citations · 23 across the 3 of their papers we have counts for
4 papers · 1 filter
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication
Matteo Perotti, Yichao Zhang, Matheus Cavalcante +2
Dense Matrix Multiplication (MatMul) is arguably one of the most ubiquitous compute-intensive kernels, spanning linear algebra, DSP, graphics, and machine learning applications. Th…
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference
MohammadHossein AskariHemmat, Theo Dupuis, Yoan Fournier +8
In this paper, we present Quark, an integer RISC-V vector processor specifically tailored for sub-byte DNN inference. Quark is implemented in GlobalFoundries' 22FDX FD-SOI technolo…
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters
Gianna Paulin, Matheus Cavalcante, Paul Scheffler +4
Modern high-performance computing architectures (Multicore, GPU, Manycore) are based on tightly-coupled clusters of processing elements, physically implemented as rectangular tiles…
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters
Matheus Cavalcante, Domenic Wüthrich, Matteo Perotti +2
While parallel architectures based on clusters of Processing Elements (PEs) sharing L1 memory are widespread, there is no consensus on how lean their PE should be. Architecting PEs…