22 citations · 32 across the 2 of their papers we have counts for
2 papers
cs.PL2023★ 10 cited
VeriGen: A Large Language Model for Verilog Code Generation
Shailja Thakur, Baleegh Ahmad, Hammond Pearce +4
In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by generating high-quality Verilog code, a common language for designing and mo…
cs.CR2022★ 22 cited
Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design
Baleegh Ahmad, Wei-Kai Liu, Luca Collini +9
To help prevent hardware security vulnerabilities from propagating to later design stages where fixes are costly, it is crucial to identify security concerns as early as possible,…