activity
20242026
collaborators

8 papers

cs.AR2026

FlexViT: A Flexible FPGA-based Accelerator for Edge Vision Transformers

Hubert Dymarkowski, Xingjian Fu, Rappy Saha +2

Deploying Vision Transformer (ViT) models on edge platforms remains challenging due to their high computational demands and the architectural heterogeneity of modern hybrid ViT mod…

cs.AR2026

Defeat the Heap: Zero-Copy Data Movement in AXI4MLIR

Elam Cohavi, Nicolas Bohm Agostini, Jude Haris +3

As custom hardware accelerators become increasingly central to machine learning workloads, efficient data transfer is critical for maximizing accelerator performance on linear alge…

cs.AR2026

Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA

Vinamra Sharma, Xingjian Fu, Jude Haris +1

Designing FPGA-based accelerators for modern artificial intelligence workloads requires exploring a large and complex hardware design space that involves architectural parameters,…

cs.AR2026

PoTAcc: A Pipeline for End-to-End Acceleration of Power-of-Two Quantized DNNs

Rappy Saha, Jude Haris, Nicolas Bohm Agostini +2

Power-of-two (PoT) quantization significantly reduces the size of deep neural networks (DNNs) and replaces multiplications with bit-shift operations for inference. Prior work has s…

cs.AR2026

LLM-Driven Design Space Exploration of FPGA-based Accelerators

Vinamra Sharma, Xingjian Fu, Jude Haris +1

Designing field-programmable gate array (FPGA)-based accelerators for modern artificial intelligence workloads requires navigating a large and complex hardware design space encompa…

cs.AR2025

F-BFQ: Flexible Block Floating-Point Quantization Accelerator for LLMs

Jude Haris, José Cano

Large Language Models (LLMs) have become increasingly prominent for daily tasks, from improving sound-totext translation to generating additional frames for the latest video games.…