5 papers
An MLIR-Based Compilation Framework for Control Flow Management on Coarse Grained Reconfigurable Arrays
Yuxuan Wang, Cristian Tirelli, Giovanni Ansaloni +2
Coarse Grained Reconfigurable Arrays (CGRAs) present both high flexibility and efficiency, making them well-suited for the acceleration of intensive workloads. Nevertheless, a key…
Mapping code on Coarse Grained Reconfigurable Arrays using a SAT solver
Cristian Tirelli, Laura Pozzi
Emerging low-powered architectures like Coarse-Grain Reconfigurable Arrays (CGRAs) are becoming more common. Often included as co-processors, they are used to accelerate compute-in…
SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures
Cristian Tirelli, Lorenzo Ferretti, Laura Pozzi
Coarse-Grain Reconfigurable Arrays (CGRAs) are emerging low-power architectures aimed at accelerating compute-intensive application loops. The acceleration that a CGRA can ultimate…
Monomorphism-based CGRA Mapping via Space and Time Decoupling
Cristian Tirelli, Rodrigo Otoni, Laura Pozzi
Coarse-Grain Reconfigurable Arrays (CGRAs) provide flexibility and energy efficiency in accelerating compute-intensive loops. Existing compilation techniques often struggle with sc…
SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs
Cristian Tirelli, Juan Sapriza, Rubén RodrÃguez Ãlvarez +6
Coarse-Grain Reconfigurable Arrays (CGRAs) represent emerging low-power architectures designed to accelerate Compute-Intensive Loops (CILs). The effectiveness of CGRAs in providing…