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cs.AR2026
Residual GPU Cache State on Apple M4 Pro
Faruk Alpay, Baris Basaran
Apple silicon exposes unified CPU-GPU memory, but the cache state left after a completed GPU command is not documented. This paper characterizes that phase boundary on a 14-core Ap…
cs.AR2026
Non-Uniform L2 Cache Latency Across the Streaming Multiprocessors of an NVIDIA L40
Faruk Alpay, Baris Basaran
The NVIDIA L40 exposes a 96 MiB L2 cache usually modeled as one uniform pool with a single hit latency. We show this is wrong at the granularity a kernel sees: L2-hit latency depen…