4 citations · 4 across the 2 of their papers we have counts for
2 papers
cs.AR2022★ 4 cited
Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL
Adel Ejjeh, Vikram Adve, Rob Rutenbar
High Level Synthesis (HLS) tools, like the Intel FPGA SDK for OpenCL, improve design productivity and enable efficient design space exploration guided by simple program directives…
cs.AR2007
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters
Yu-Tsun Chien, Dong Chen, Jea-Hong Lou +3
This paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the…