6 papers
High-Performance NTT Accelerators for PQC leveraging Unified Redundant Arithmetic and Fine-Tuned Microarchitecture
George Alexakis, Dimitrios Schoinianakis, Giorgos Dimitrakopoulos
Post-quantum cryptography and privacy-preserving technologies are expected to play a central role in future secure communication systems. Lattice-based PQC schemes such as ML-KEM (…
Low-Cost Multi-Precision Systolic Arrays for Accelerating FHE NTTs on AI ASICs
George Alexakis, Dimitrios Schoinianakis, Giorgos Dimitrakopoulos
Fully Homomorphic Encryption (FHE) ensures robust data privacy but suffers from prohibitive computational overhead. Accelerating FHE on AI hardware like Tensor Processing Units (TP…
MPX: A Unified Systolic Array for Matrix and Polynomial Multiplication
George Alexakis, Dimitrios Schoinianakis, Giorgos Dimitrakopoulos
Polynomial multiplication is a fundamental kernel in Fully Homomorphic Encryption (FHE) and post-quantum cryptography (PQC) and is commonly accelerated through Number Theoretic Tra…
High-Performance Pipelined NTT Accelerators with Homogeneous Digit-Serial Modulo Arithmetic
George Alexakis, Dimitrios Schoinianakis, Giorgos Dimitrakopoulos
The Number Theoretic Transform (NTT) is a fundamental operation in privacy-preserving technologies, particularly within fully homomorphic encryption (FHE). The efficiency of NTT co…
Efficient Implementation of RISC-V Vector Permutation Instructions
Vasileios Titopoulos, George Alexakis, Chrysostomos Nicopoulos +1
RISC-V CPUs leverage the RVV (RISC-V Vector) extension to accelerate data-parallel workloads. In addition to arithmetic operations, RVV includes powerful permutation instructions t…
Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs
Vasileios Titopoulos, George Alexakis, Kosmas Alexandridis +2
The deployment of Machine Learning (ML) applications at the edge on resource-constrained devices has accentuated the need for efficient ML processing on low-cost processors. While…